The structure of the instructions in the YASEP architecture

The YASEP uses a 16-bits fixed-format instruction word that can be extended with a 16-bits immediate field or a 16-bits extended word. This instruction format is identical for both YASEP16 and YASEP32 : YASEP32 can use short (16-bits) instructions and YASEP16 can use long (32-bit) instructions. There is very little difference and the instruction decoder must handle both instruction lengths.

Each instruction can contain :

• 2 flag bits (16/32 bit flag and immediate flag)
• an opcode (6 bits)
• up to 4 register addresses (4 bits each)
• a 4, 6, 16 or 20-bit sign-extended immediate value
• a condition code (3 bits)
• auto-increment/decrement flags (2 or 4 bits)

These fields and flags are not all used at the same time. Some combinations are impossible by construction, some others don't make sense, others can be hidden by the assembler. However, a wide variety of instructions (an opcode followed by register names, immediate data or other flags) can be written by the user. This page explains what the "instruction forms" are, how they are designed and when they are used.

Summary

An "instruction form" is named after the way it is written in assembly language. It is a sequence of letters that describe each used field :

• R for a register
• i for a short immediate number (4 or 6 bits)
• I for a long immediate value (16 or 20 bits)

The YASEP allows only a limited number of forms. The two least significant bits of each instruction determine how to interpret the operands and other fields. The 2 bits create 4 combinations :

• [00] Short form (16 bits) with 2 registers (RR)
• [10] Short form (16 bits) with 1 register and one signed 4-bit immediate value (iR)
• [01] Immediate Long form (32 bits) with 2 registers and one signed 16-bit immediate value (IRR)
• [11] Extended long form (32 bits) with 3 registers (RRR), predicate and post-incrementation.

The extended form contains an auxiliary flag aux to allow two sub-forms : the si4 field may be used either as a register address (RRR) or as an immediate 6 bits signed value. (iRR).

A few opcodes such as MOV have only one operand and may use the unused snd register address field to create a 20-bits signed immediate value.

Overall, instructions might use one of 6 physical forms. The assembler can make more forms available to the programmer by using certain combinations with unused fields.

Notes about the Imm4 field

Just like the Imm16 field, the Imm4 field provides a signed integer.

However, if the instruction is part of the SHL group (bit shuffling: rotations and shifts) then the field is considered as a positive integer. This preserves the compatibility between the YASEP16 and YASEP32 for the ranges from 0 to 15. For shift amounts larger than 15 with YASEP32, use the long form with Imm16 or the extended form with Imm6.

Where do the results go ?

The YASEP instructions write the result of an operation (when any) to a register whose address is given by the snd or dst fields, depending on the instruction form :

• When the instruction is short (RR, iR etc.), the result is written to snd.
• When the instruction's form is "long extended" (RRR, iRR etc.) or "long immediate" (IRR, IR...) then the result is written to dst.

This system could eventually make architectural development difficult in the far future. However, this is required to keep the instructions compact. Furthermore, in the datapath, what really counts (for performance) is the access time of the operands, not the destination address which can be computed at the same time as the ALU (a good dozen of logic levels). Since the architecture does not bypasse the pipeline (the microYASEP waits until a register is written before reading it again), we have more freedom with the fields and we can get the most out of each bit, while still keeping the instructions orthogonal. The assembler puts each field at the right position place for us.

The "short forms"

Let's start with the most simple instruction forms. The short instructions have their LSB cleared and are 16-bit long. This is enough for another flag, a 6-bit opcode and two 4-bit fields.

• The first 4-bit field is always a register address, named snd because it is used as a source, can undergo negation of all the bits (for subtractions and boolean operations) and it is generally used as destination.
• The second 4-bit field is interpreted as a sign-extended immediate value (from -8 to 7) when the 2nd LSB is set to 1, or as a register address when the 2nd LSB is 0. It is called si4 because it is used as source or immediate (4 bits) operand.

"Short register form" : Two register addresses

1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0
S				SND				OPCODE						I/R	S/L
R2				R1				ADD						0	0

 

"Short immediate form" : one immediate and one register address

1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0
S				SND				OPCODE						I/R	S/L
-3				R1				ADD						1	0

In practice, these 2 combinations can be used in 5 ways in assembly language, since any of these fields can be more or less useful depending on the kind of operation :

Form "RR" : Register to Register

 ADD R1 R2   ; R2 <- R1+R2

Form "iR" : short immediate to Register

 ADD 2 R3   ; R3 <- 2+R3

 PUT 3 R1   ; Write the content of R1 into Special Register #3

Form "R" : Register

 NEG R1   ; internally : R1 <- 0 - R1

Form "i" : short Immediate

 CRIT 3   ; disable the interrupts during the 3 following instructions

Form "ALONE" : no operand

 NOP   ; Nop operand needed, all fields ignored.

The "long forms"

The YASEP interprets the instruction as 32-bit long when the LSB is set to 1. The 16 lower bits are similar to the short forms. The second LSB selects how to interpret the following half-word :

• When it is cleared, the additional field is a 16-bit sign-extended immediate value (ranging from -32768 to 32767) that is used as a source for the operation.
  2011-09-17: YASEP32 defines the IMM20 flag that adds 4 more immediate bits for instructions that don't use the snd field.
• When it is set, it is an extended field that provides more register addresses, auto-incrementation and predicates.

"Long immediate form" : Two register addresses and one long immediate value

DST				IMM16   15:0																SND				OPCODE						I16	S/L
R1				1234h																R2				ADD						0	1
3 1	3 0	2 9	2 8	2 7	2 6	2 5	2 4	2 3	2 2	2 1	2 0	1 9	1 8	1 7	1 6	1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0

Form "IRR" : long Immediate and Register to Register

 ADD 1234h R2 R1   ; R1 <- 1234h + R2

Form "IR" : long Immediate to Register

 GET 1234h R1   ; R1 <- SR[1234h]

; Both are encoded the same way and perform the same operation :
 OR 1234h R1 R1
 OR 1234h R1

.profile YASEP32 ; the 4 MSB are ignored with YASEP16
 CALL 12345h R1
 MOV  12345h R1

 PUT 12345h R1   ; Write the content of R1 into Special Register #12345h

The "extended forms"

The extended forms reuse the short form's structure and add 16 bits for several additional features :

• A dedicated destination register field dst (bits 28 to 31) that overrides the short form's destination (snd becomes only a source)
• An auxiliary Imm6 flag (since the Immediate/Register flag selects the extended form)
• A source register used for comparisons and conditions (cnd at bits 24 to 27)
• A condition selection field (3 bits) (the instructions is always executed when it's cleared)
• 2 to 4 bits for pointer updates
• A 6-bits signed immediate fiels, sharing bits with si4 and the update flags.

"Extended Register form" : three register addressess

DST				CND				code			aux	upd				S				SN				OPCODE						E/I	S/L
R3				0				0			0	0				R2				R1				ADD						1	1
3 1	3 0	2 9	2 8	2 7	2 6	2 5	2 4	2 3	2 2	2 1	2 0	1 9	1 8	1 7	1 6	1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0

 

Form "RRR" : Register and Register to Register

 ADD R1 R2 R3 ; R3 <- R1+R2

"Extended Immediate form" : two register addressess and one 6-bits immediate field

DST				CND				code			aux	upd		Imm6						SN				OPCODE						E/I	S/L
R3				0				0			1	0		25						R1				ADD						1	1
3 1	3 0	2 9	2 8	2 7	2 6	2 5	2 4	2 3	2 2	2 1	2 0	1 9	1 8	1 7	1 6	1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0

 

Form "iRR" : imm6 and Register to Register

 ADD 25 R1 R3 ; R3 <- R1+25

Condition codes

The extended instructions contain 7 bits that encode the condition under which the result of the current operation is written back/validated. These bits encode 3 types of predicates :

• When the function code is 01, the 4-bits address field cnd gives the index of a bit to read/select from a "shadow register" (a copy of R1 or I/O pins, to be determined).
• Otherwise, if cnd=0000 (the address of the PC register), then the function selects between "Always" (1), Carry and Equal.
• Finally, the address is that of a register. The condition might be either its least significant bit (LSB) of this register, its most significant bit (MSB) or a OR-combine of all the bits (to check is the register is cleared).

Tables of the condition codes

cnd=0 (PC)

Fonction	Neg=0	Neg=1
00	Always (default)	Never (reserved)
01	BIT1 (Shadow[0]!=0)	BIT0 (Shadow[0]=0)
10	CARRY / NO_BORROW (Carry flag is set)	NO_CARRY / BORROW (Carry flag cleared)
11	EQ (Equal flag is set)	NEQ (Equal flag cleared)

The condition codes are designed so the condition "ALWAYS" is represented with all the bits cleared (0).

All the conditions can be negated. The condition "NEVER" is created with inverting the condition "ALWAYS".

The "shadow" register is currently undefined. In the first iterations, it can be a copy of the R1 register. Later it can be configured to access I/O pins for example.

Auto-updates

The extended instruction forms contain an additional field that is dedicated to "pointer auto-update" and the format is defined since 2014-01-31. Some values might change a bit in the future (while the system is being tuned) but the bit field will not move anymore. See the justifications at Definition of the auto-update fields.

The YASEP implementations that don't support this feature (for example, the microYASEP) should trigger an exception when something else than NOP is encountered.

These bits are decoded in the context of the Aux flag since it makes no sense to modify si4 when it contains immediate values. The remaining 4 or 2 bits contain the most useful combinations of parameters, which should increase code density.

Pre-incrementation and pre-decrementation are not available for architectural reasons. Let's imagine that it was possible to pre-compute an address before the actual operation starts, within a single instruction:
- this would increase the instruction's latency, as the memory should be fetched and this would delay the actual execution by an unknown number of clock cycles
- the generated address could trigger a page fault or protection fault, but there is no way to stop the instruction's execution in the middle, or even resume the pipeline with partial data.

The post-update system follows these implicit rules:

• Normal R registers are incremented or decremented by 1.
• When a D register address is found, the corresponding A register gets updated. D registers must be modified explicitly.
• The amount of increment of a A register depends on the size of the accessed data:
  • For YASEP16, the increment is 2
  • For YASEP32, the increment is 4
  • For the IB, EZB et ESB instructions (that handle bytes), the increment is 1
  • For the IH, EZH et ESH instructions (that handle half-words), the increment is 2

Some combinations require special care:

ADD R1 R2 R3+  ; R3 is not incremented and contains the sum of R1 and R2

ADD R1+ R1+ R2   ; R1 is incremented only once
ADD D1+ D2+ D1+  ; A1 is incremented only once

As a consequence, only A registers can be modified by the DST field, and only implicitly by addressing its D peer.

Use

MOV 50, R1 ; set the counter for 50 iterations
MOV 0, R2  ; clear the accumulator

  ADD R1 R2 ; add the counter's value to the accumulator
ADD -2 PC NZ R1- ; If R1 is not zero then
                 ;   - decrement R1
                 ;   - jump 2 bytes backwards and continue looping

A loop, or a code block that must be skipped, can contain up to 8 long instructions or 16 short instructions, without additional operations or registers.

The YASEP can also read and write consecutive memory words without overhead because the pointer registers A can be incremented while their associated data registers D are accessed. You can copy or modify blocks of data very easily:

MOV 50, R1       ;  set the counter for 50 iterations
MOV 2345h, A1    ; set the source pointer
MOV 6789h, A2    ; destination pointer

  MOV D1+ D2+    ; copy one word
ADD -4 PC NZ R1- ; If R1 is not zero then
                 ;   - decrement R1
                 ;   - jump 4 bytes backwards and continue looping

This feature also makes stack access easy, PUSH and POP instructions are emulated. Since there is no single hardware-defined stack, the YASEP can supports languages with multiple stacks such as FORTH.