-- Inc10bits.vhd -- Generated by Actel's core generator and slightly tuned library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library proasic3; use proasic3.all; entity Inc10 is port( DataA : in std_logic_vector(9 downto 0); Sum : out std_logic_vector(9 downto 0)) ; end Inc10; architecture PA3 of Inc10 is component XOR2 port(A, B : in std_logic := 'U'; Y : out std_logic); end component; component AND3 port(A, B, C : in std_logic := 'U'; Y : out std_logic); end component; component AND2 port(A, B : in std_logic := 'U'; Y : out std_logic); end component; component INV port(A : in std_logic := 'U'; Y : out std_logic); end component; signal inc_1_net, inc_2_net, Rcout_4_net, Rcout_5_net, inc_5_net, Rcout_6_net, Rcout_7_net, inc_8_net, Rcout_8_net, inc_10_net, incb_2_net, Rcout_9_net : std_logic ; begin -- L1 INV_0_inst : INV port map(A=> DataA(0), Y=> Sum(0)); XOR2_1_inst : XOR2 port map(A=> DataA(0), B=> DataA(1), Y=> Sum(1)); XOR2_2_1_inst : XOR2 port map(A=> inc_1_net, B=> DataA(2), Y=> Sum(2)); XOR2_2_inst : XOR2 port map(A=> inc_2_net, B=> DataA(3), Y=> Sum(3)); XOR2_3_inst : XOR2 port map(A=> Rcout_4_net, B=> DataA(4), Y=> Sum(4)); XOR2_4_inst : XOR2 port map(A=> Rcout_5_net, B=> DataA(5), Y=> Sum(5)); XOR2_5_inst : XOR2 port map(A=> Rcout_6_net, B=> DataA(6), Y=> Sum(6)); XOR2_1_5_inst : XOR2 port map(A=> Rcout_7_net, B=> DataA(7), Y=> Sum(7)); XOR2_6_inst : XOR2 port map(A=> Rcout_8_net, B=> DataA(8), Y=> Sum(8)); XOR2_7_inst : XOR2 port map(A=> Rcout_9_net, B=> DataA(9), Y=> Sum(9)); -- L2 AND2_2_inst : AND2 port map(A=> DataA(0), B=> DataA(1), Y=> inc_1_net); AND2_4_inst : AND2 port map(A=> inc_2_net, B=> DataA(3), Y=> Rcout_4_net); AND2_5_inst : AND3 port map(A=> inc_2_net, B=> DataA(3), C => DataA(4), Y=> Rcout_5_net); AND2_7_inst : AND2 port map(A=> inc_2_net, B=> inc_5_net, Y=> Rcout_6_net); AND2_1_7_inst : AND3 port map(A=> inc_2_net, B=> inc_5_net, C => DataA(6), Y=> Rcout_7_net); AND2_1_8_inst : AND3 port map(A=> incb_2_net, B=> inc_5_net, C => inc_8_net, Y=> Rcout_8_net); -- fanout changed here fAND2_8_inst : AND3 port map(A=> incb_2_net, B=> inc_5_net, C => inc_10_net, Y=> Rcout_9_net); -- L3 AND2b_9_inst : AND3 port map(A=> DataA(0), B=> DataA(1), C => DataA(2), Y=> incb_2_net); AND2_3_inst : AND3 port map(A=> DataA(0), B=> DataA(1), C => DataA(2), Y=> inc_2_net); AND2_6_inst : AND3 port map(A=> DataA(3), B=> DataA(4), C => DataA(5), Y=> inc_5_net); AND2_8_inst : AND2 port map(A=> DataA(6), B=> DataA(7), Y=> inc_8_net); AND2_9_inst : AND3 port map(A=> DataA(6), B=> DataA(7), C => DataA(8), Y=> inc_10_net); end PA3; architecture rtl of Inc10 is begin Sum<=std_logic_vector( unsigned(DataA) + 1); end rtl;